Details for the labs available in the department:
Different labs in the department are :
- National Instruments LabView Laboratory
- Robotics & Industrial Automation Laboratory
- Texas Instruments Laboratory
- Analog electronics & Communication Laboratory
- LIC and Communication Laboratory
- Embedded System Laboratory
- Digital Signal Processing Laboratory
- Logic Design Laboratory
- VLSI Laboratory
- Advanced Digital Communication Laboratory
- Python Programming Laboratory
Small write up of 50-100 words about the lab:
In technical education, it is highly required that the students are exposed to more of hands-on-practices, and are involved in the application part of the theoretical knowledge. The labs in the Department of Electronics and Communication Engineering are well equipped, for the under-graduate course and post-graduate course along with Research and Development in the institute. Department has various Centres of Excellence (CoEs) which include Robotics & Industrial Automation, National Instruments Labview Academy, Texas Instruments. Overall these laboratories enable students to develop the capabilities to design, simulate, develop, fabricate and test electronic circuits/systems.
Different types of practicals/experiments carried out in each lab:
Research Lab
The Research and Development (R&D)centre of ECE is established in the year 2017, with the aim of excelling to create the state-of-the-art facilities for various Research and Development activities.The R&D centre is all set to motivate and encourage the faculty and students to carry out research work, generate project proposals, to tap funds from governmental and industrial funding agencies and establish centresof Excellence in the college as well as to interact with industries. Currently R& D activities are being carried out in the areas viz. VLSI, Image Processing, Embedded System Design and IoT, 3D printing, Robotics, PCB Design and Communication.
National Instruments LabView Laboratory
- This LabVIEW academy is used to train and certify faculty and students on the LabVIEW Platform.
- Students are using this lab to develop final year projects.
- Students are encouraged and trained to participate in NI YANTRA event, which will be organized by National Instruments.
- On completion of course / workshop, Certified LabVIEW ASSOCIATE DEVELPOER (CLAD) exam will be conducted and certificate will be issued after clearing CLAD exam.
- Three faculties (Dr. Brindha M, Ms. Aparna P & Mr. Sheik Karemullah) are Certified Lab VIEW Associate Developer.
- Five Students have cleared the CLAD exam with 85% marks.
Robotics & Industrial Automation Laboratory
- Robotics and Industrial Automation laboratories was established in association with Robolab Technologies Pvt. Ltd.
- One week training program has been organized for students & faculty members.
- Facilities are essentially meant for students & research activities
- The students will learn an hands on experiences on Mobilio, Hexa crawler, Omibo, Martian Rover Prototype, JCBian, Flexo Hand Robot and Quadcopter.
Texas Instruments Laboratory
- The Department of Electronics and Communication engineering (ECE) has signed a Memorandum of Understanding (MOU) with Edgate Technologies (Pvt) ltd, for establishing a Texas Instruments (TI) analog lab.
- As a part of the MOU, Edgate Technologies (Pvt) ltd had sent the TIVA launch pad (15 Nos) and booster pack (5 Nos) to setup the Texas Instruments TIVA lab.
- Further, a Faculty Development Programme has been conducted to improve the programming knowledge of faculties in Texas Instrument (TI) processors (i.e., TIVA series processors).
Analog electronics & Communication Laboratory
| Sl.No | PART A : Hardware Experiments |
|---|---|
| 1 | Wiring of RC coupled Single stage FET & BJT amplifier and determine the gain-frequency response, input and output impedances |
| 2 | Wiring of BJT Darlington Emitter follower with and without bootstrapping and determination of the gain, input and output impedances. |
| 3 | Design an oscillator with tank circuit having two inductances and one capacitance and compare the practical frequency with theoretical frequency. |
| 4 | Design an oscillator with tank circuit having two capacitance and one inductance and compare the practical frequency with theoretical frequency. |
| 5 | Conduct experiment to test diode clipping (single/double ended) and clamping circuits (positive/negative). |
| 6 | Design an Oscillator using FET whose tank circuit produces a total phase shit of 180, and calculate the frequency of output waveform. |
| 7 | Design an oscillator whose frequency is 2MHZ and compare with the theoretical frequency. |
| 8 | Find a suitable power amplifier that removes the cross over distortion and calculate the efficiency |
Analog electronics & Communication Laboratory
| Sl.No | PART-B : Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus, CircuitLab or any other equivalent tool can be used) |
|---|---|
| 1 | RC Phase Shift Ocsillator |
| 2 | Colpitts And Hartley Oscillator |
| 3 | Crystal Oscillator |
| 4 | Precision Half and Full wave Rectifier |
LIC Laboratory
| Sl.No | PART A : Hardware Experiments |
|---|---|
| 1 | Design Adder, Integrator and Differentiator using Op-Amp. |
| 2 | Design an instrumentation amplifier of a differential mode gain of “A” using three Amplifiers. |
| 3 | Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values and obtain the hysteresis |
| 4 | Design of RC Phase shift and Wien’s bridge oscillators using Op-amp. |
| 5 | To set up and study a triangular waveform generator using Op-amp for 1kHz frequency |
| 6 | Design active second order Butterworth low pass and high pass filters |
| 7 | Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from toggle switches and (ii) by generating digital inputs using mod-16 counter. |
| 8 | Design of Monostable and Astable Multivibrator using 555 Timer. |
| PART-B: Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus, Circuit Lab or any other equivalent tool can be used) | |
| 9 | RC Phase shift oscillator using Op-amp. |
| 10 | Band-pass Filter and Narrow band-reject filter using Op-amp |
| 11 | Relaxation oscillator using using Op-Amp. |
| 12 | Monostable and Astable Multivibrator using 555 Timer. |
Analog electronics & Communication Laboratory
| Sl.No | PART-A: |
|---|---|
| 1 | ALP to multiply two 16 bit binarynumbers. |
| 2 | ALP to find the sum of first 10 integernumbers. |
| 3 | ALP to find the number of 0’s and 1’s in a 32 bitdata |
| 4 | ALP to find determine whether the given 16 bit is even orodd |
| 5 | ALP to write data toRAM |
| Sl.No | PART-B: |
| 6 | Display “Hello world” message using internalUART |
| 7 | Interface and Control the speed of a DCMotor. |
| 8 | Interface a Steppermotor and rotate it in clockwise and anti-clockwise direction. |
| 9 | Interface a DAC and generate Triangular and Squarewaveforms. |
| 10 | Interface a 4x4 keyboard and display the key code on anLCD. |
| 11 | Demonstrate the use of an external interrupt to toggle an LEDOn/Off. |
| 12 | Display the Hexdigits0 to Fona7-segment LEDinterface, with anappropriate delay. |
| 13 | Measure Ambient temperature using a sensor and SPI ADCIC. |
Digital Signal Processing Laboratory
| Sl.No | PART-A : |
|---|---|
| 1 | Verification of sampling theorem (use interpolation function). |
| 2 | Linear and circular convolution of two given sequences, Commutative, distributive and associative property of convolution. |
| 3 | Auto and cross correlation of two sequences and verification of their properties |
| 4 | Solving a given difference equation. |
| 5 | Computation of N point DFT of a given sequence and to plot magnitude and phase spectrum (using DFT equation and verify it by built-in routine). |
| 6 | (i) Verification of DFT properties (like Linearity and Parseval’s theorem, etc.) (ii) DFT computation of square pulse and Sinc function etc. |
| 7 | Design and implementation of Low pass and High pass FIR filter to meet the desired specifications (using different window techniques) and test the filter with an audio file. Plot the spectrum of audio signal before and after filtering. |
| 8 | Design and implementation of a digital IIR filter (Low pass and High pass) to meet given specifications and test with an audio file. Plot the spectrum of audio signal before and after filtering. |
| Following Experiments to be done using DSP kit | |
| 9 | Obtain the Linear convolution of two sequences. |
| 10 | Compute Circular convolution of two sequences. |
| 11 | Compute the N-point DFT of a given sequence. |
| 12 | Determine the Impulse response of first order and second order system. |
| 13 | Generation of Sine wave and standard test signals |
Logic Design Laboratory
| Sl.No | PART A- Rig up the circuit for the following and verify on IC Trainer Kit. |
|---|---|
| 1 | Verify (a) Demorgan’s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. |
| 2 | Design and implement (a) Full Adder using basic logic gates. (b) Full subtractor using basic logic gates. |
| 3 | (a) Design and implement (i) 4-bitParallelAdder/ Subtractor using IC 7483. (ii) BCD to Excess-3 code conversion and vice-versa. |
| 4 | Realize (i) Adder &Subtractors using IC 74153 (ii) 4-variable function using IC 74151(8:1MUX) |
| 5 | Realize the following flip-flops using NAND Gates.(a) Clocked SR Flip-Flop (b) JK Flip-Flop (c) D-Flip-Flop |
| 6 | Realize the following shift registers using IC7474 |
| 7 | (a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring Counter (f) Johnson Counter. |
| 8 | Realize (i) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop (ii) Mod-N Counter using IC7490 / 7476. |
| PART B- Simulate the following using Verilog Code and Implement on FPGA | |
| 9 | Write a Verilog program for the following combinationaldesigns a) 2 to 4 decoder b) 8 to 3 (encoder without priority & with priority) c) 8 to 1 multiplexer d) 4 bit binary to grayconverter e) Multiplexer, De-multiplexer, Comparator |
| 10 | Design 4 bit binary, BCD counters with Synchronous reset and asynchronous reset and “any sequence”counters using Verilog code. |
| 11 | Write HDL code to display messages on alpha numeric LCD display. |
| 12 | Write a HDL code to control speed, direction of DC and Stepper motor. |
| 13 | Write HDL code to interface Hex key pad and display the key code on seven segment display. |
| 14 | Write a HDL code to accept Analog signal, Temperature sensor and display the data on LCD or Seven Segment Display. |
VLSI Laboratory
| Sl.No | Part – A- Analog Design Use any VLSI design tools to carry out the experiments, use library files and technology files below 180 nm. |
|---|---|
| 1 | a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out the following: a. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and time period of 20ns and plot the input voltage and output voltage of designed inverter? b. From the simulation results compute tpHL, tpLH and td for all three geometrical settings of width? c. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter b)Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and LVS,extract parasitic and perform post layout simulations, compare the results with pre-layout simulations. Record the observations. |
| 2 | a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS inverter computed in experiment 1. Verify the functionality of NAND gate and also find out the delay td for all four possible combinations of input vectors. Table the results. Increase the drive strength to 2X and 4X and tabulate the results. b)Draw layout of NAND withWp/Wn = 40/20, use optimum layout methods. Verify for DRC and LVS,extract parasitic and perform post layout simulations, compare the results with pre-layout simulations. Record the observations. |
| 3 | a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its transient response and AC response? Measures the Unity Gain Bandwidth (UGB), amplification factor by varying transistor geometries, study the impact of variation in width to UGB. b) Draw layout of common source amplifier, use optimum layout methods. Verify for DRC and LVS,extract parasitic and perform post layout simulations, compare the results with pre-layout simulations. Record the observations. |
| 4 | a)Capture schematic of two-stage operational amplifier and measure the following: a. UGB b. dB bandwidth c. Gain margin and phase margin with and without coupling capacitance d. Use the op-amp in the inverting and non-inverting configuration and verify its functionality e. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the stage wise transistor geometries and record the observations. b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in 180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in 4.a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout simulations. Record the observations |
| Part – B Digital Design Carry out the experiments using semicustom design flow or ASIC design flow, use technology library 180/90/45nm and below Note: The experiments can also be carried out using FPGA design flow, it is required to set appropriate constraints in FPGA advanced synthesis options | |
| 5 | Write verilog code for 4-bit up/down asynchronous reset counter and carry out the following: a. Verify the functionality using test bench b. Synthesize the design by setting area and timing constraint. Obtain the gate level netlist, find the critical path and maximum frequency of operation. Record the area requirement in terms of number of cells required and properties of each cell in terms of driving strength, power and area requirement. c. Perform the above for 32-bit up/down counter and identify the critical path, delay of critical path, and maximum frequency of operation, total number of cells required and total area. |
| 6 | Write verilog code for 4-bit adder and verify its functionality using test bench. Synthesize the design by setting proper constraints and obtain the net list. From the report generated identify critical path, maximum delay, total number of cells, power requirement and total area required. Change the constraints and obtain optimum synthesis results. |
| 7 | Write verilog code for UART and carry out the following: a. Perform functional verification using test bench b. Synthesize the design targeting suitable library and by setting area and timing constraints c. For various constrains set, tabulate the area, power and delay for the synthesized netlist d. Identify the critical path and set the constraints to obtain optimum gate level netlist with suitable constraints |
| 8 | Write verilog code for 32-bit ALU supporting four logical and four arithmetic operations, use case statement and if statement for ALU behavioral modeling. a. Perform functional verification using test bench b. Synthesize the design targeting suitable library by setting area and timing constraints c. For various constrains set, tabulate the area, power and delay for the synthesized netlist d. Identify the critical path and set the constraints to obtain optimum gate level netlist with suitable constraints Compare the synthesis results of ALU modeled using IF and CASE statements. |
| 9 | Write verilog code for Latch and Flip-flop, Synthesize the design and compare the synthesis report (D, SR,JK). |
| 10 | For the synthesized netlist carry out the following for any two above experiments: a. Floor planning (automatic), identify the placement of pads b. Placement and Routing, record the parameters such as no. of layers used for routing, flip method forplacement of standard cells, placement of standard cells, routes of power and ground, and routing of standard cells c. Physical verification and record the LVS and DRC reports d. Perform Back annotation and verify the functionality of the design e. Generate GDSII and record the number of masks and its color composition |
Advanced Digital Communication Laboratory
| Sl.No | PART-A: Experiments No. 1 to 5 has to be performed using discrete components. |
|---|---|
| 1 | Amplitude Modulation andDemodulation: |
| 2 | Frequency modulation and demodulation (IC 8038/2206 can beused) |
| 3 | Pulse sampling, flat top sampling and reconstruction |
| 4 | Time Division Multiplexing and Demultiplexing of two band limited signals. |
| 5 | FSK and PSK generation and detection |
| 6 | Measurement of frequency, guide wavelength, power, VSWR and attenuationin micro wave test bench. |
| 7 | Obtain the Radiation Pattern and Measurement of directivity and gain of microstrip dipole and Yagi antennas. |
| 8 | Determination of a. Coupling and isolation characteristics of microstrip directionalcoupler. b. Resonance characteristics of microstrip ring resonator and computation of dielectric constant of thesubstrate. c. Power division and isolation of microstrip powerdivider. |
| PART-B: Simulation Experiments using SCILAB/MATLAB/Simulink or Lab VIEW | |
| 9 | Simulate NRZ, RZ, half-sinusoid and raised cosine pulses and generate eye diagram for binary polar signaling |
| 10 | Pulse code modulation and demodulation system |
| 11 | Computations of the Probability of bit error for coherent binary ASK, FSK and PSK for an AWGN Channel and Compare them with their Performancecurves. |
| 11 | Digital Modulation Schemes i)DPSKTransmitterandreceiver ii)QPSKTransmitterandReceiver. |
Python Programming Laboratory
| Sl.No | PART-A: Experiments No. 1 to 5 has to be performed using discrete components. |
|---|---|
| 1 | Print all the Disarium numbers between 1 and 100. |
| 2 | Encrypt the text using Caesar Cipher technique. Display the encrypted text. Prompt the user for input and the shift pattern. |
| 3 | Perform Jump Search for a given key and report success or failure. Prompt the user to enter the key and a list of numbers. |
| 4 | The celebrity problem is the problem of finding the celebrity among n people. A celebrity is someone who does not know anyone (including themselves) but is known by everyone. Write a Python program to solve the celebrity problem. |
| 5 | Construct a linked list. Prompt the user for input. Remove any duplicate numbers from the linked list. |
